	// verilator_coverage annotation
	module reg_mem_wb(
 020001	    input  wire clk,
%000001	    input  wire rst,
 000259	    input  wire[31:0] me_mem_data,
 000658	    input  wire[31:0] me_alu_o,
 000083	    input  wire[4:0]  me_rd,
 000013	    input  wire       me_mem2reg,
 000023	    input  wire       me_regs_write,
 000272	    output reg[31:0]  wb_mem_data,
 000659	    output reg[31:0]  wb_alu_o,
 000081	    output reg[4:0]   wb_rd,
 000013	    output reg        wb_mem2reg,
 000024	    output reg        wb_regs_write,
	    
%000002	    input wire me_m_write,
%000003	    output reg wb_m_write,
 000038	    input wire [1:0] me_m_w_index,
 000037	    output reg [1:0] wb_m_w_index,
%000419	    input wire[31:0] me_matrix_mopa_o[3:0],
%000419	    output reg[31:0] wb_matrix_mopa_o[3:0],
%000003	    input wire me_matrix_mopa_en,
%000003	    output reg wb_matrix_mopa_en
	);
	
	always @(posedge clk) begin
 000100	    if (!rst)begin
	        wb_mem_data    <= 0;     
	        wb_alu_o       <= 0;     
	        wb_rd          <= 0; 
	        wb_mem2reg     <= 0;     
	        wb_regs_write  <= 0;   
	        wb_m_write     <= 0;     
	        wb_m_w_index     <= 0;    
	        wb_matrix_mopa_o[0] <= 0;
	        wb_matrix_mopa_o[1] <= 0;
	        wb_matrix_mopa_o[2] <= 0;
	        wb_matrix_mopa_o[3] <= 0;  
	        wb_matrix_mopa_en <= 0;
	    end 
 009900	    else begin
	        wb_mem_data    <= me_mem_data;     
	        wb_alu_o       <= me_alu_o;     
	        wb_rd          <= me_rd; 
	        wb_mem2reg     <= me_mem2reg;     
	        wb_regs_write  <= me_regs_write;  
	        wb_m_write     <= me_m_write; 
	        wb_m_w_index     <= me_m_w_index;
	        wb_matrix_mopa_o[0] <= me_matrix_mopa_o[0];
	        wb_matrix_mopa_o[1] <= me_matrix_mopa_o[1];
	        wb_matrix_mopa_o[2] <= me_matrix_mopa_o[2];
	        wb_matrix_mopa_o[3] <= me_matrix_mopa_o[3];
	        wb_matrix_mopa_en <= me_matrix_mopa_en;
	    end
	    $display("wb_mem_data  : %h",wb_mem_data);
	    $display("wb_alu_o     : %h",wb_alu_o);
	    $display("wb_mem2reg   : %h",wb_mem2reg);
	    $display("wb_regs_write: %h",wb_regs_write);
	end
	
	endmodule
	
